ELEC 498 Proposal:

 

Design, Verification and Implementation of a Floating Point Coprocessor.

 

 

Submitted By:

 

Group #2

Hock Lee Ooi

Michael Wood

Fadi Yared

 

Faculty Supervisor:

 

Dr. A Afsahi

 

October 15 2002

EXECUTIVE SUMMARY

 

The MC68HC11 micro-controller produced by Motorola is ideal for many control applications; however, it is not capable of floating point arithmetic. This document proposes the design of a floating point coprocessor for the MC68HC11.  The proposed Floating Point Unit (FPU) will provide the MC68HC11 with fast and accurate means for floating point addition, subtraction, multiplication and division in the IEEE-754 floating point standard.  The proposed FPU will be implemented on the Altera UP1 Education Board which is based on the MAX7000 and FLEX10K chips.

 

Both the MC68HC11 and the Altera UP1 Education Board are components of Queen’s ECE program.  The development software, evaluation hardware and considerable reference materials are available from Queen’s ECE by authorized checkout; consequently, this proposal forecasts no development costs.

 

Dr. Ahmed Afsahi stated: “Any ingenious scientific application uses floating point arithmetic.”  The proposed FPU coprocessor will greatly increase the capability of the MC68HC11 and could be used by Queen’s for many applications, such as Queen’s Solar Car.  The most promising aspect of this project is as groundwork for future development.  A future year’s project could expand the FPU’s capabilities to integration, convolution and other advanced functions.

 

 

TABLE OF CONTENTS

1      INTRODUCTION.. 4

1.1       Purpose. 4

1.2       Work Objectives. 4

1.3       Work Scope. 5

2      FUNCTIONAL DESCRIPTION.. 5

2.1       General 5

2.2       Interface. 6

2.3       Performance. 6

3      DESIGN AND PRODUCTION APPROACH.. 7

3.1       Process. 7

3.2       Division of Labour 8

4      TESTING AND EVALUATION.. 9

5      RESOURCE REQUIREMENTS. 9

5.1       Scheduling. 9

5.2       Material and Other Resources. 10

6      CONCLUSIONS. 11

7      REFERENCES. 11

 

1         INTRODUCTION

 

1.1    Purpose

 

This document is intended to summarize, for departmental approval, the ELEC 498 project undertaken by Hock Lee Ooi, Michael Wood and Fadi Yared.  The intended audience is Dr. Peter J. McLane, Dr. Michael J. Korenberg, Dr. Mohamed M. Bayoumi, Pawel A. Dmochowski, and Dr. Ahmad Afsahi.

 

1.2    Work Objectives

 

The MC68HC11 is a powerful single chip micro-controller produced by Motorola. It has a concise instruction set combined with six addressing modes, true bit manipulation, 16-bit arithmetic operations and a second 16-bit index register.  These features make it ideal for control applications requiring both high speed I/O and high speed calculations.

 

Some applications can be implemented using the 16-bit integer precision of the MC68HC11; however, many applications and algorithms require more precise values and hence require floating point math. 

 

The purpose of this project is to design, simulate, implement, and verify a floating point coprocessor for the MC68HC11.  This Floating Point Unit (FPU) should provide the MC68HC11 with fast and accurate means for floating point math.

 

The design and implementation of the FPU will be accomplished using MAX+PLUS II VHDL CAD software and an Altera UP1 Education Board.  The UP1 Education Board is a stand-alone experiment board based on two Altera devices:  MAX7000 and FLEX10K.  These are programmable logic devices capable of supporting an FPU design and an interface to other chips such as the MC68HC11.

 

1.3    Work Scope

 

This project entails both hardware and software design. 

 

The FPU will be designed in simulation software to be capable of four basic 32 bit functions (add, subtract, multiply and divide) according to the IEEE-754 floating point standard.  The FPU will also provide a communication interface for the MC68HC11.  This interface will: 

  1. Accept an 8 bit op-code and a series of 32 bit operands.
  2. Return a 32 bit result.  

 

Software routines (fadd, fsub, fmul, fdiv) will be developed for the MC68HC11 which will send operands to the FPU and retrieve the results.

 

Finally the completed designs will be implemented in a MC68HC11EVB (an evaluation board) and the Altera UP1 Education Board.

 

2         FUNCTIONAL DESCRIPTION

 

2.1    General

 

The majority of the proposed product is a fully integrated and tested FPU to be used in conjunction with the Motorola 68HC11 micro controller.  The unit will greatly enhance the capability of the Micro controller by adding the ability to perform High precision arithmetic.  The physical product will be designed via MAX+PLUS II CAD tools and programmed into a programmable logic device (PLD).

 

In addition to the FPU, an interface protocol will be designed.  This entails two components that can be separated into hardware and software considerations.  The hardware component involves building interface circuitry that would allow for a communication protocol between the FPU and micro controller (handshaking).  The software component requires programming the micro controller with the ability to utilize the handshaking protocol.

 

The testing process consists of simulation that will occur at both the software and hardware levels.  The process will involve isolated and integrated simulation of the FPU design via CAD tools.  Once the FPU has been simulated and verified independently of the microcontroller, it will again be tested and simulated in conjunction with the additional interface circuitry.  Performing the simulation task in this way is necessary since physical limitations of the circuitry may affect the validity of the FPU results.

 

2.2    Interface

 

The user interface to the FPU will be done through the microcontroller.  This implies that the user interface is the preexisting interface to the MC68HC11 with the additional FPU instructions.  Once the appropriate instructions have been programmed into the controller, the user will assemble code with the new instructions (fadd, fsub, fmul, fdiv) available as subroutines.  For proper operation it will be required that the user provides two 32-bit numbers stored in the X and Y registers of the micro controller.  Once the FPU calculates the result it will be placed in a reserved portion of memory available for the user to access.  These floating-point operations will be handled according to the IEEE-754 standard. 

 

2.3    Performance

 

The FPU interface with the MC68HC11 will operate in accordance with the existing specifications of the MC68HC11.  These are as follows:

-  Up to 5 MHz bus operation at 5 V

-  Up to 3 MHz bus operation at 3 V

-  Two 8-bit or one 16-bit accumulator

-  Two 16-bit index registers

-  16-bit stack pointer

-  Addressing:  Immediate, Direct, Extended, Indexed, Inherent, and Relative

-  Memory mapped I/O and special functions

-  Serial and Parallel communications ports

 

In addition the FPU will operate on the Altera UP1 Education Board with 7 – 12 v DC at a minimum of 250mA.  The internal clock available on the FPU is 25.175 MHz.

 

3         DESIGN AND PRODUCTION APPROACH

 

3.1    Process

 

First, MAX+PLUS II will be used to design a unit capable of 32 bit addition according to the IEEE-754 floating point standard.  Definitions of IEEE-754 and algorithms for floating point math are available from ELEC 374 course material and a computer arithmetic text book, both provided by Dr. Ahmed Afsahi. 

 

Second, a communications interface between the Altera and Motorola chips will be established.  Material on the MC68HC11’s communication abilities is available from ELEC 371 course material and Motorola texts, available from Queen’s ECE Tech Services.  This interface will send data over an 8 bit parallel line, using full handshaking.  A software implementation of this interface for the MC68HC11 will be designed and tested using QEVB11 simulation software.  A supporting hardware implementation of the implementation of this interface will be designed and tested in MAX+PLUS II.  Because the communication interface is integral to the usefulness of the project, it will be implemented and tested in hardware before further capabilities are designed.  The Altera UP1 Education Board and MC68HC11EVB are available from Queen’s ECE Tech Services.

 

After verification of the communications interface, the remaining functions will be implemented in MAX+PLUS II, supporting software will be written in QEVB11, and the final design will be tested and verified in the hardware evaluation boards.

 

The software for the MC68HC11 will be written to occupy a reserved block of user memory.  For each of the subroutines, the user will be required to have preloaded X and Y registers with the addresses of two 32 bit operands.  The subroutine will handle all communications with the FPU and write the result to an address specified in memory at the end of the reserved software block.

 

3.2    Division of Labour

 

This project has no partners in industry, but Faculty Supervisor Ahmed Afsahi supports the project and is available for consultation.  The division of labor is summarized in the table below.  (X) = primary. (x) = partial.  (–)  = slight.

 

Task

Lee

Mike

Fadi

Research IEEE-754 standard and associated floating point addition algorithms.

X

–

x

Implement floating point addition in MAX+PLUS II and test by waveform simulation.

X

–

x

Research the communication abilities of MC68HC11

–

X

x

Implement a communication interface in QEVB11 and test by simulation.

–

x

X

Implement a complementary communication interface in MAX+PLUS II and test by waveform simulation.

–

X

x

Write the fadd subroutine for the MC68HC11

x

–

X

Test and verify floating point addition using the Altera UP1 Education Board and MC68HC11EVB

x

x

x

Research floating point subtraction algorithms.

X

–

–

Research floating point multiplication algorithms.

–

–

X

Research floating point division algorithms.

–

X

–

Implement floating point subtraction in MAX+PLUS II and test by waveform simulation.

X

–

–

Implement floating point multiplication in MAX+PLUS II and test by waveform simulation.

–

x

X

Implement floating point division in MAX+PLUS II and test by waveform simulation.

–

X

x

Test and verify all features using the Altera UP1 Education Board and MC68HC11EVB

x

x

x

 

4         TESTING AND EVALUATION

 

Functional and timing simulation in MAX+PLUS II will provide the first testing of the FPU.  The waveform simulation results will be examined to verify the correctness and accuracy of the floating point operations.  Inputs for all four operations will be chosen as expected, boundary and illegal (according to the IEEE-754 standard).

 

Once the communications interface between the two devices has been developed, testing of the operations will be carried out in the hardware.  A software testing program will be written for the MC68HC11 which will use telnet to allow users to specify an operation and operands and view the result.  Again expected, boundary and illegal inputs will be tested for all four operations.

 

Performance will be tested in the final product, by counting the clock cycles required for each subroutine (fadd, fsub, fmul, fdiv) to run from call to completion.  This will require small modification to the testing software.  In order to test the performance of the FPU independent of the communications channel, a fifth op-code will be created which sets the FPU into testing mode.  After the FPU has received this op-code, it will return the time it required to calculate a result instead of the result.  This will require some extra development of the FPU.

 

5         RESOURCE REQUIREMENTS

 

5.1    Scheduling

 

Milestone

Begin

Complete

Floating point addition in MAX+PLUS II

Oct. 1

Nov. 10

Communication interface in QEVB11.

Oct. 1

Nov. 10

Communication interface in MAX+PLUS II.

Oct. 1

Nov. 10

Verify floating point addition using the Altera UP1 Education Board and MC68HC11EVB

Nov. 10

Nov. 30

Floating point subtraction in MAX+PLUS II

Jan. 1

Jan. 30

Floating point multiplication in MAX+PLUS II

Jan. 1

Feb. 30

Floating point division in MAX+PLUS II

Jan. 1

Feb. 30

Verify all features using the Altera UP1 Education Board and MC68HC11EVB

Mar. 1

Mar. 30

 

5.2    Material and Other Resources

 

No sun accounts will be required for this project. Bain Lab will be sufficient for all work that cannot be done out of the home; therefore, no special labs or lab time need be booked.  The Altera and Motorola evaluation boards will be required on November 10-30 and March 1-30.  This may conflict with ELEC 371 in the fall term. 

 

All of the required resources listed below are available from Dr. Ahmed Afsahi, Queen’s ECE course material, or Queen’s ECE tech services.  The Motorola boards and books and the Altera board can be signed out from Queen’s ECE tech services at not cost.  The total cost of this project consists of unpredicted and incidental fees, and therefore should be under fifty dollars.

 

  • QEVB11 simulation software is required for the design and testing of the MC68HC11 software.  This is available at no cost from Queen’s ECE department.
  • MAX+PLUS II simulation software is required for the design and testing of the FPU.  This is available on the machines in Queen’s Bain Lab.
  • Altera UP1 Education Board is required for verification of the system in hardware.  This is available for authorized check-out from Queen’s ECE Tech Services.
  • A text book on Computer Arithmetic and ELEC 374 course material and is required for definitions of IEEE-754 and algorithms for floating point math.
  • Motorola texts for the MC68HC11 and ELEC 371 course material is required for aid in design of the necessary MC68HC11 software.  The Motorola texts are available for authorized check-out from Queen’s ECE Tech Services.

 

6         CONCLUSIONS

 

The proposed Floating Point Unit (FPU) coprocessor will provide the MC68HC11 with the capability for floating point addition, subtraction, multiplication and division in the IEEE-754 floating point standard.  It will be implemented on the Altera UP1 Education Board, and promises to increase the applicability of the MC68HC11 to include many applications requiring the 32 bit floating point precision.

 

Both the MC68HC11 and the Altera UP1 Education Board are components of Queen’s ECE program.  The development software, evaluation hardware and considerable reference materials are available from Queen’s ECE by authorized checkout; consequently, this proposal forecasts no development costs.

 

The proposed FPU coprocessor will greatly increase the capability of the MC68HC11 and could be used by Queen’s for many applications, such as Queen’s Solar Car.  The most promising aspect of this project is as groundwork for future development.  A future year’s project could expand the FPU’s capabilities to integration, convolution and other advanced functions.  Such a device could be used by developers in the Queen’s community, or even in ECE undergraduate program courses.

 

7         REFERENCES

 

-         Computer Arithmetic: algorithms and hardware designs, Behrooz Parhami, Oxford University Press, 2000.

-         Altera University Program Design Laboratory Package, http://www.ece.queensu.ca/hpages/courses/ELEC374/upds.pdf

-         Microprocessor Systems using the Motorola 68HC11, Naraig Manjikian Campus Bookstore 1813, 2001.

-         Dr. Ahmed Afsahi (consultation).